1. Field of the Invention
This invention relates to the field of chopper-stabilized amplifiers, particularly high bandwidth, low noise chopper-stabilized amplifiers.
2. Description of the Related Art
Chopper-stabilized operational amplifiers (CSAs) are well known and widely used due to their low input offset voltages. A schematic diagram of a basic CSA 5 is shown in FIG. 1a. The CSA receives a differential input signal at terminals 10 and 12, which are connected to the non-inverting and inverting terminals, respectively, of a main operational amplifier A1. A "memory" capacitor C1 is connected to A1's null terminal N1, and A1's output is the output of the CSA. An auxiliary operational amplifier A2 has its non-inverting input connected to differential input terminal 10 through a switch S1, and to its inverting terminal through a switch S2. A2's inverting terminal is also connected to differential input terminal 12. A memory capacitor C2 is connected to A2's null terminal N2. A switch S3 is connected between A2's output and C2, and a switch S4 is connected between A2's output and A1's null terminal N1.
A clock circuit 14 produces two outputs 16 and 18 which are the inverse of each other, and which oscillate between two phases .phi.1 and .phi.2. A timing diagram of clock outputs 16 and 18 is shown in FIG. 1b. Clock output 16 controls switches S1 and S4, opening them during .phi.1 and closing them during .phi.2. Clock output 18 controls switches S2 and S3, closing them during .phi.1 and opening them during .phi.2. Clock outputs 16 and 18 are the CSA's "chopping signals" and the frequency at which they oscillate is the CSA's "chopping frequency".
The operation of the CSA is as follows: during .phi.1, switch S2 closes and shorts the inputs of auxiliary amplifier A2 together. Switch S3 is also closed, connecting A2's output to its nulling input N2, thus nulling A2. The voltage on N2 is stored on memory capacitor C2. The differential input signal is amplified by A1 alone during .phi.1.
During .phi.2, S2 opens and S1 closes, connecting A2's inputs across differential input terminals 10 and 12. Switch S3 also opens, but A2 continues to be nulled by the voltage stored on C2. Switch S4 closes, connecting A2's output to A1's null input N1. Now a differential input to the CSA is amplified by A2 followed by A1 through N1. When the gain of A2 is large, the CSA's input offset voltage is largely determined by A2, and because A2 was nulled during .phi.1, the CSAs has a very low input offset voltage. Memory capacitor C1 connected to A1's nulling input N1 allows A1 to continue to be nulled during .phi.1.
Chopper-stabilized amplifiers have several drawbacks, however, as are discussed, for example, in Horowitz and Hill, The Art of Electronics, Cambridge University Press (1989), pp. 416-417. One of the most serious is a clock-induced "input-referred" noise caused by charge coupling from the switches, typically MOSFETs, causing spikes to appear in the CSA's output at the chopping frequency f.sub.c. Intermodulation distortion (IMD) is also present in the output due to the differences in the CSA's gain between .phi.1 and .phi.2. The gain bandwidths during .phi.1 and .phi.2 are typically made as equal as possible to minimize IMD. Some mismatch is inevitable, however, and IMD is present as a consequence.
The usual approach to reduce input-referred noise and IMD is found in U.S. Pat. No. 4,931,745 to Goff et al. Here, the chopping frequency f.sub.c is made as high as can be accommodated by the settling time of memory capacitors C1 and C2, pushing noise and IMD to the highest frequency possible. However, a component of IMD exists at f.sub.c -f.sub.s, where f.sub.s is the frequency of the input signal. IMD and chopping noise can be filtered as long as they are outside the signal band, but the input signal bandwidth is practically limited to about f.sub.c /2. Input signal frequency range can be extended by increasing f.sub.c, but if the chopping frequency is too high, the memory capacitors cannot settle sufficiently and the offset voltage will shoot up. Another disadvantage of clocking the amplifier at a fixed frequency is that the IMD and chopping noise are concentrated into a fixed frequency band, reducing the amplifier's spurious free dynamic range.
An alternative approach was disclosed in U.S. Pat. No. 5,115,202 to Brown. A pseudo-random binary sequence generator (PRBS) acts as a clock circuit in order to reduce the power spectral density of the residual IMD and clock noise by dynamically randomizing the chopping rate. This scatters the IMD components and clock noise over a wide frequency range, reducing their power spectral density. However, the low frequency input-referred noise of the CSA is raised significantly with this technique. The amplitude of the low frequency noise is approximately inversely proportional to the square root of the chopping frequency. Brown's approach allows the instantaneous chopping frequency to approach DC, and thus significantly raise the noise floor.